Wireless devices have been in use for many years for enabling mobile communication of voice and data. Such devices can include mobile phones and wireless enabled personal digital assistants (PDA's) for example. FIG. 1 is a generic block diagram of the core components of such wireless devices. The wireless core 10 includes a base band processor 12 for controlling application specific functions of the wireless device and for providing and receiving voice or data signals to a radio frequency (RF) transceiver chip 14. The RF transceiver chip 14 is responsible for frequency up-conversion of transmission signals, and frequency down-conversion of received signals. RF transceiver chip 14 includes a receiver core 16 connected to an antenna 18 for receiving transmitted signals from a base station or another mobile device, and a transmitter core 20 for transmitting signals through the antenna 18. Those of skill in the art should understand that FIG. 1 is a simplified block diagram, and can include other functional blocks that may be necessary to enable proper operation or functionality.
Generally, the transmitter core 20 is responsible for up-converting electromagnetic signals from base band to higher frequencies for transmission, while receiver core 16 is responsible for down-converting those high frequencies back to their original frequency band when they reach the receiver, processes known as up-conversion and down-conversion (or modulation and demodulation) respectively. The original (or base band) signal, may be, for example, data, voice or video. These base band signals may be produced by transducers such as microphones or video cameras, be computer generated, or transferred from an electronic storage device. In general, the high frequencies provide longer range and higher capacity channels than base band signals, and because high frequency radio frequency (RF) signals can propagate through the air, they are preferably used for wireless transmissions as well as hard-wired or fibre channels.
All of these signals are generally referred to as radio frequency (RF) signals, which are electromagnetic signals; that is, waveforms with electrical and magnetic properties within the electromagnetic spectrum normally associated with radio wave propagation.
As shown in FIG. 2, the receiver core 16 can include a low noise amplifier 30, a mixer 32, a filter 34, a variable gain amplifier 36, and an analog to digital converter (ADC) 38. Filter 34 is typically a 6th order filter consisting of a combination of transconductance cells, transconductance-capacitor filters, MOS-capacitor filters, RC filters, and op-amp circuits. ADC 38 can be implemented as either a discrete time or continuous time architecture. For example, ADC 38 can be implemented as a delta-sigma ADC with multi-level feedback digital to analog conversion. Additional circuits can preferably include dummy filter circuit 40 and dummy ADC circuit 42. Generally, dummy filter circuit 40 is a replica of filter circuit 34, or a replica of components of filter circuit 34, that will monitor an electrical parameter of filter 34 and tune it should the output value vary due to process and/or temperature variations. Similarly, dummy ADC circuit 42 is a replica of ADC 38, or a replica of components of ADC 38, and monitors an electrical parameter of ADC 38 for tuning purposes. Two separate dummy circuits are required because the architectures of the filter circuit 34 and the ADC 38 are distinct and different.
The function of the receiver core 16 is as follows. An RF input signal RFin is amplified by low noise amplifier 30, and then down-converted to baseband frequency z by mixer 32. This down-converted baseband signal is then filtered through filter 34 to reduce the dynamic range of the signal, and then amplified to a desired level of gain by variable gain amplifier 36 in response to the level of gain control voltage VCONT. The resulting output signal RFout is then converted to a digital signal D_SIGNAL by ADC 38. The digital signal D_SIGNAL can now be further processed in the digital domain by downstream circuits, such as base band processor 12.
This listing of components in receiver core 16 is not comprehensive, and any person of skill in the art will understand that the specific configuration will depend on the communication standard being adhered to and the chosen receiver architecture.
At the present time, all the aforementioned components of the receiver core 16 shown in FIG. 2 function in the analog domain, meaning that they are configured and operated for analog signal processing of the RF input signal RFin. Preferably, the quality of the signal received at ADC 38 should be maximized, in order to minimize potential data errors being transferred digitally to the baseband processor. The signal quality becomes more important as radio technology improves, hence it is important to ensure that the receiver components can execute their intended functions.
One receiver component that can affect signal quality is filter 34. Filter 34 being an analog circuit, suffers from typical analog circuit problems. For example, the circuit transfer functions can vary between identical circuits on the same chip, and can vary from chip to chip. The varying coefficients of the transfer function of filter 34 will adversely affect its characteristics, such as its phase and pass band shape, for example. Another limitation of filter 34 is that its design in the analog domain is limited to specific types of filters. Types of filters can include an FIR filter or an IIR filter, which are well known in the art. Accordingly, not all desired filters can be implemented or synthesized, for optimal signal processing.
From a manufacturing cost perspective, analog circuits do not scale well with each process generation. Digital circuits on the other hand are easily scalable. Therefore, mixed circuits will tend to be dominated in size by the analog circuits, unnecessarily increasing the area of the device. Ultimately, due to the limited capability of implementing optimal filter functions in the analog domain, signal quality can suffer.
In contrast, almost any type of filter can be synthesized in the digital domain. Thus, high signal quality can be obtained since compensation techniques and linear circuit behaviour can be achieved with digital circuits. Therefore, there is a trend to implement as much of the circuit components of FIG. 2 in the digital domain.
For the receiver path shown in FIG. 2, one desired configuration that maximizes the amount of digital domain circuitry is shown in FIG. 3. In this desired configuration, amplifier 30, mixer 32, ADC 38 and dummy ADC 40 remain in the analog domain. Filter 34, variable gain circuit 36, and dummy filter 42 of FIG. 2 have been ported to the digital domain 44 as digital filter 46, and digital gain circuit 48 respectively. The configuration shown in FIG. 3 represents an architecture that maximizes the amount of digital circuitry. Those of skill in the art will understand that such a receiver path configuration would be simpler to implement as there are less analog components than the receiver path shown in FIG. 2.
Unfortunately, the desired configuration of FIG. 3 is very difficult to achieve with presently known circuits and technology. Mainly, because there is no pre-filtering of the down-converted RF input signal before ADC 38, ADC 38 must then be able to accommodate the large dynamic range associated with the RFin signal. In particular, for single bit feedback configurations, delta-sigma ADC technology is more suitable for higher dynamic range signals. However, a major drawback of delta-sigma ADC's is that the clock used in the ADC 38 must be very clean, meaning that any minor clock jitter can contribute to increased sampling error. Increased sampling error will ultimately result in unreliable operation of the wireless device. Unfortunately, a suitable ADC circuit capable of reliable operation for large dynamic ranges is not yet available. Hence, for present mixed analog-digital receiver path designs, signal filtering is still required prior to ADC 38. However, a 6th order analog filter, such as filter 34 in FIG. 2, consumes a relatively large amount of silicon area and has variations and limitations on its frequency response due to the previously discussed inherent limitations of an analog filter circuit implementation. Thus, signal quality is compromised.
The clock jitter problem has been addressed in the prior art by using a multi-level feedback DAC within the sigma-delta ADC. However, a significant problem with using multi-level feedback DAC is the added complexity and power consumption of the sigma-delta ADC.
Wireless devices are preferably low power to maximize battery life, and small to be packed into progressively shrinking form factor devices. Therefore, the current wireless core receiver path design shown in FIG. 2 is not suitable for future low power and minimally sized wireless devices. On the other hand, short-term foreseeable technology does not appear to be available to maximize the digital portion of a hybrid analog-digital receiver core. Accordingly, the all-analog receiver core shown in FIG. 2 remains the most reliable receiver core architecture available.
It is, therefore, desirable to provide a wireless receiver core architecture that will accommodate high dynamic range RF input signals while maximizing the amount of digital domain circuits to improve signal quality and to reduce receiver core power consumption.